Liquid crystal displays

ABSTRACT

A data line and an amorphous silicon pattern are formed on a substrate. The first electrode pattern is extended from the data line and overlaps an edge of the amorphous silicon pattern. The second electrode pattern is made of the same metal as the first electrode pattern and overlaps the edge of the amorphous silicon pattern at an opposite side of the first electrode pattern. Edges of the first and the second electrode patterns are sharply formed so that a tunneling effect easily occurs through the amorphous silicon pattern. An indium-tin-oxide pattern for a capacitor is formed at the end of the second electrode pattern. The capacitor is formed between the ITO pattern and a common electrode.

BACKGROUND OF THE INVENTION

[0001] (a) Field of the Invention

[0002] The present invention relates to liquid crystal displays(referred to as an LCD hereinafter) and manufacturing methods thereof,and more particularly, to circuits for preventing electrostaticdischarge which are provided in the LCD and manufacturing methodsthereof.

[0003] (b) Description of the Related Art

[0004] A liquid crystal display (LCD), which is one type of flat paneldisplay (FPD), includes two substrates having transparent electrodes anda liquid crystal layer interposed between the substrates. In the LCD,light transmittance is controlled by varying the voltages applied to theliquid crystal layer.

[0005] On a thin film transistor (TFT) substrate of the LCO, N gatelines and M data lines, which cross each other, define a plurality ofpixels in an N×M matrix. A pixel electrode is formed in each of thepixels and the pixel electrode is connected to the gate and the datalines through a switching device such as the TFT. The TFT controlsdisplay signals transmitted through the data line according to thestates of the scanning signals transmitted through the gate line

[0006] The majority of the LCD manufacturing process is performed on aglass substrate. Since the glass substrate is nonconductive, electriccharges, which are abruptly generated on the substrate, cannot bedispersed. This may cause the insulating films or TFTs to become damagedby the electrostatic discharge.

[0007] In the LCD manufacturing process, since the electrostaticcharges, which is generated after the step of assembling the TFTsubstrate and a color filter substrate is completed, cause high voltageseven though the amount of the charges are small, the quality of thesubstrate decreases. In addition, since the electrostatic charge isusually generated during the step of cutting the substrate. then flowinto an active area having the pixel regions through gate and data pads,the channels of the TFTs near the pads become damaged by theelectrostatic discharge with easy.

[0008]FIG. 1 shows a layout view of the conventional LCD substrate whichis damaged by an electrostatic discharge. As shown in the drawing, theLCD panel includes a TFT substrate 10 and a color filter substrate 20. Apad area 30, in which pads are formed to connect each wire of the TFTsubstrate 10 to driving circuits, and an active area 40, in which actualimages are displayed, are separately formed on the TFT substrate 10.

[0009] Lines 50 in the active area 40 illustrate pixels having somedefects by damaged TFT portions. If electrostatic charges are generatedin the pad area 30 and moves inside the active area 40, the channels ofthe TFTs, which are located near the pads, become damaged, or thequality of the channels is deteriorated.

[0010] The deteriorated TFT is shown in FIG. 2. As shown in the drawing,a gate line 60 and a data line 80 cross each other, and an edge of agate electrode 61, extended from the gate line 60, overlaps an end of asource electrode 81 which is extended from the data line 80. An edge ofthe gate electrode 61, opposite the edge overlapping with the sourceelectrode 81, overlaps with a drain electrode 82. A semiconductor film70 is formed on the overlapping portion of the gate electrode 61, sourceelectrode 81 and drain electrode 82.

[0011] If the electrostatic charges enter into the TFT, comprised of thesemiconductor film 70, the source and drain electrodes 81 and 82, andthe gate electrode 61, sparks occur between the source and the drainelectrodes 81 and 82, thereby damaging the semiconductor film 70.

[0012] To limit to the LCD by electrostatic discharge, a shorting bar,through which all metal wires are connected, is widely used fordispersing the electrostatic charges. However, in the case where anamount of the electric charges is large, it is not possible tocompletely prevent damage caused by the electrostatic discharge.Moreover, after the shorting bar is removed, it is not possible toprevent the electrostatic charges from entering into the substrate.

[0013] In manufacturing the LCD panel having the above structure,polarizers are attached after performing a visual display test byapplying test signals to the shorting bar. Next, the main substrate iscut into individual LCO substrates, a liquid crystal material isinjected between the substrates. and the injection holes are sealed. Theshorting bar is removed in the step of cutting the substrate. In anothervisual display test, different test signals are applied to adjacent datalines by using probes directly contacted to each of the pads, thendriving circuits are attached to the LCD panel.

[0014] As mentioned above, since the shorting bar is removed in the samestep of cutting the substrate. it is difficult to protect the substrateagainst the electrostatic charges after the step of removing theshorting bar. Moreover, since the polarizers are attached after thesimple test, in which only one signal is applied to every wire, by usingthe shorting bar, there is a high possibility that the polarizers areattached even on the damaged LCD panel. If the damaged panel is detectedin the post-test, the panel, along with the expensive polarizers has tobe discarded, thereby increasing overall manufacturing costs of the LCD.

SUMMARY OF THE INVENTION

[0015] It is an object of the present invention to provide a liquidcrystal display having a substrate which is protected againstelectrostatic charges, regardless of the strength thereof.

[0016] It is another object of the present invention to provide a liquidcrystal display which prevents electrostatic charges from entering intothe substrate after a shorting bar is removed, thereby minimizing pixeldefects.

[0017] It is yet another object of the present invention to provide amanufacturing method of a liquid crystal display in which an LCD panelis prevented from becoming damaged by an electrostatic discharge. whilemanufacturing costs of the LCD are reduced.

[0018] To achieve the above objects, the present invention provides aliquid crystal display in which a plurality of spark inducing circuits,which extinguish electrostatic charges generated in wires of a TFTsubstrate, and electrostatic charging circuits, which charge theelectrostatic charges and extinguish the same, are formed on a TFTsubstrate.

[0019] The spark inducing circuit includes a plurality of the TFTs,connected in series between two adjacent wires and gate electrodes ofwhich are connected to one another; and two capacitors, one electrode ofwhich is connected to the gate electrode of the TFTs and the otherelectrode of which is connected to the adjacent wire. Since a pluralityof the spark inducing circuits are connected in parallel between theadjacent wires, if electrostatic charges generate in the wires, sparksoccur in the TFTs of the spark inducing circuits and high voltagecurrent is induced between the source and the drain electrode of theTFTs. This surge current loses its strength by being changed into jouleheat. Therefore, the TFTs in an active area are protected from theelectrostatic discharge. It is also possible for the electrostaticcharges generated in the wires to be dispersed. The spark inducingcircuit is formed such that the TFT connects to the capacitor betweeneach wire and a common electrode in series.

[0020] In another aspects, the spark inducing circuit may include a TFT,a gate electrode and a drain electrode of which are respectivelyconnected to the same wire, and a source electrode of which is connectedto a dummy line, and a capacitor which is formed between the wire andthe drain electrode.

[0021] Meanwhile, a circuit for dispersing electrostatic charges, whichcomprises a resistor and a capacitor connected in series between a dataline and a dummy gate line; and another resistor connected between anadjacent data line of the data line and the capacitor, may be usedinstead of the spark inducing circuit.

[0022] The electrostatic charging circuit includes a first electrostaticcharging circuit, which is formed outside a sealing material by which aTFT substrate and a corresponding substrate are assembled to each other,and a second electrostatic charging circuit, which is formed inside asealing material. The first electrostatic charging circuit has twocapacitors which connect to each other between two adjacent wires inseries. A plurality of the first electrostatic charging circuits may beconnected to the adjacent wires in parallel. The second electrostaticcharging circuit, for preventing electrostatic charges from enteringinside the active area, includes capacitors which are formed betweeneach wire and a common electrode. The capacitor includes an additionalcorresponding electrode connected to the common electrode and the wires.The corresponding electrode which corresponds to the gate line of thewires is made of a metal used for forming the data line, and thecorresponding electrode which corresponds to the data line of wires ismade of a metal used for forming the gate line. The first and the secondelectrostatic charging circuits charge and remove the electrostaticcharges generating in the wires.

[0023] To protect the TFT substrate from electrostatic charges. ashorting bar, which links all the wires formed on the TFT substrate, isformed inside a cutting line of the substrate. Since the shorting barremains on the substrate even after the TFT substrate is divided into aplurality LCD panels, it is still possible for the TFT substrate to beprotected by the shorting bar.

[0024] To protect the LCD from electrostatic charges occurring in themanufacturing process, a electrostatic discharge protection circuit, aTFT and wires are formed in a substrate, a shorting bar is formed insidethe cutting line of the substrate, and the substrate is cut to bedivided into several TFT substrates. Next, individual LCD panels areformed and the shorting bar is removed by edge-grinding. After visualdisplay tests are performed by applying test signals to each of thewires, polarizers are attached on the LCD panel on which no defect isdetected. Driving circuits are then connected to the LCD panels.

[0025] In the manufacturing method of the LCD, it is possible to protectthe LCD panel against electrostatic charges generated during themanufacturing process since the step of cutting the substrate, ofinjecting liquid crystals and of sealing an injection hole are performedwhile the shorting bar remains on the LCD panel. Moreover, it ispossible to reduce manufacturing costs since polarizers are attached ononly the good LCD panels.

[0026] In another embodiment of the present invention, dummy lines areformed outside a visual active area which is defined by a plurality ofpixels, the pixels being formed by a plurality of dummy pixels by theintersections of gate and data lines and the dummy lines. A dummy TFTconnecting the dummy line is formed in each dummy pixel

[0027] In the above, the ratio of the width to the length of the dummyTFT channel is larger than the ratio of the width to the length of theTFT channel, which is formed in the active area, or one or more dummyTFTs are formed in the dummy pixel. Accordingly, electrostatic chargesare dispersed through the dummy TFT when the same is generated.

[0028] A dummy pixel electrode, which is connected to the TFT, is formedin the dummy pixel, and a black matrix which covers the dummy pixel isformed on one of two substrates.

[0029] Generally, since electrostatic charges, which generate at thebeginning or end of each step. passes through the dummy gate and datalines which define the dummy pixels surrounding the active area,deterioration caused by electrostatic charges occur in the dummy TFTfirst. Therefore, the TFTs, which are formed inside the active area andconnected to the gate and the data line, are protected againstelectrostatic charges. Here, damage to the dummy pixels does not affectthe quality of the LCD.

[0030] The shape of the dummy TFT may be changed to effectively induceelectrostatic charges. It is preferable that the ratio of the width tothe area of the dummy TFT channel is bigger than the ratio of the widthto the area of the TFT. A plurality of dummy TFTs may be formed in thedummy pixel.

[0031] Meanwhile, a electrostatic charge dispersing pattern, consistingof two electrodes and a semiconductor pattern, is formed outside anactive area to discharge electrostatic charges through the channel ofthe semiconductor pattern. To effectively discharge electrostaticcharges, the ends of the electrodes may be pointedly formed and itpreferable to form a capacitor in the end of the semiconductor pattern.A plurality of the discharging patterns may be connected to a wire, ortwo wires, in parallel.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a layout view of a conventional liquid crystal display(LCD) substrate which is damaged by an electrostatic discharge;

[0033]FIG. 2 is an enlarged layout view of the thin film transistor inFIG. 1;

[0034]FIG. 3 is a schematic diagram of a LCD substrate according to apreferred embodiment of the present invention;

[0035]FIG. 4 is an enlarged layout view of A in FIG. 3 according to afirst preferred embodiment of the present invention;

[0036]FIG. 5 illustrates an equivalent circuit of an electrostaticdischarge protection diode circuit shown in FIG. 4;

[0037]FIG. 6 is an enlarged layout view of A in FIG. 3 according to asecond preferred embodiment of the present invention;

[0038]FIG. 7 is an equivalent circuit of a first spark inducing circuitin FIGS. 5 and 6;

[0039]FIG. 8 is an equivalent circuit of a second spark inducing circuitin FIGS. 5 and 6;

[0040]FIG. 9 is an equivalent circuit of a third spark inducing circuitin FIGS. 5 and 6;

[0041]FIG. 10 is an equivalent circuit of a fourth spark inducingcircuit in FIGS. 5 and 6:

[0042]FIG. 11 is an equivalent circuit of a first electrostatic chargingcircuit in FIGS. 5 and 6;

[0043]FIG. 12 is an equivalent circuit of a second electrostaticcharging circuit in FIGS. 6 and 7;

[0044]FIG. 13 is a layout view of a pattern of the fourth spark inducingcircuit of FIG. 10;

[0045]FIG. 14 is a cross sectional view taken along line XIV-XIV′ ofFIG. 13;

[0046]FIG. 15 is a layout view of another pattern of the fourth sparkinducing circuit of FIG. 10.

[0047]FIG. 16 is a cross sectional view taken along line XVI-XVI′ ofFIG. 15;

[0048]FIG. 17 is a layout view of a dummy pixel for dischargingelectrostatic charges according to a preferred embodiment of the presentinvention;

[0049]FIG. 18 is a cross sectional view taken along line XVIII-XVIII′ ofFIG. 17;

[0050]FIG. 19 is a layout view of a dummy pixel for dischargingelectrostatic charges according to another preferred embodiment of thepresent invention;

[0051]FIG. 20 is a layout view of a pattern for dischargingelectrostatic charges according to a first preferred embodiment of thepresent invention;

[0052]FIG. 21 is a cross sectional view taken along line XXI-XXI′ ofFIG. 20;

[0053]FIG. 22 is a perspective view of a capacitor formed in an end ofthe pattern for discharging electrostatic charges;

[0054]FIG. 23 is a layout view of a pattern for dischargingelectrostatic charges according to a second preferred embodiment thepresent invention;

[0055]FIG. 24 is a layout view of a pattern for dischargingelectrostatic charges according to a third preferred embodiment of thepresent invention;

[0056]FIG. 25 is a layout view of a pattern for dischargingelectrostatic charges according to a fourth preferred embodiment of thepresent invention;

[0057]FIGS. 26A to 26F are cross sectional views used to describe amanufacturing method of the patterns for discharging electrostaticcharges of the first to third embodiments of the present invention;

[0058]FIG. 27 is an equivalent circuit of a circuit for preventingelectrostatic charges which is connected to a portion of A in FIG. 3according to a third preferred embodiment of the present invention;

[0059]FIG. 28 is a layout view of the pattern of the circuit in FIG. 27;

[0060]FIG. 29 is a cross sectional view taken along line XXIX-XXIX′ ofFIG. 28;

[0061]FIG. 30 is a layout view of the pattern of the circuit forpreventing an electrostatic discharge which is connected to a portion ofA in FIG. 3 according to a fourth preferred embodiment of the presentinvention;

[0062]FIG. 31 is a cross sectional view taken along line XXXI-XXXI′ inFIG. 30;

[0063]FIG. 32 is a layout view of the pattern of the circuit forpreventing an electrostatic discharge which is connected to a portion ofA in FIG. 3 according to a fifth preferred embodiment of the presentinvention;

[0064]FIG. 33 is a perspective view of an LCD showing a state in which athin film transistor substrate and a color filter substrate areassembled to each other; and

[0065]FIG. 34 is a flow chart showing a manufacturing method of an LCDaccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0066] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. In the drawings, the thickness of layers and regionsare exaggerated for clarity. Like numbers refer to like elementsthroughout. It will be understood that when an element such as a layer,region or substrate is referred to as being “on” another element, it canbe directly on the other element or intervening elements may also bepresent.

[0067] Referring first to FIG. 3, shown is a schematic diagram of aliquid crystal display substrate according to a preferred embodiment ofthe present invention. As shown in FIG. 3, a plurality of gate lines 100are formed on a transparent insulating substrate 10 in a horizontaldirection, and gate pads 101 are formed at the ends of respective gatelines 100. A plurality of data lines 200 are formed in a verticaldirection to cross the gate lines 100, and data pads 201 are formed atthe ends of respective data lines 200. Thin film transistors (TFTs),which are switching devices are formed in respect pixel regions PXsdefined by intersections of the gate and data lines 100 and 200. Thegathering of a plurality of the pixel regions PX is an active area,confined by an active area line 41, where the visual image is displayed.

[0068] Shorting bars 102 and 202, which respectively link all the gatelines 100 and all the data lines 200 at ends thereof, are formed nearedges of the substrate 10. The shorting bars 102 and 202 areinterconnected such that the gate and the data lines 100 and 200 areelectrically connected. As a result, if electrostatic charges aregenerated in the gate and data pads 101 and 201, the electrostaticcharges are dispersed through the shorting bars 102 and 202.

[0069] In the case that the electrostatic charges have a high electriccharge value, the electrostatic charges may nevertheless enter into theactive area, even with the shorting bars 102 and 202 being provided asdescribed above. In addition, if electrostatic charges are generatedafter the shorting bars 102 and 202 are removed along a cutting line 11,the electrostatic charges easily enter the active area. To effectivelydisperse the electrostatic charges, electrostatic charge dispersingcircuits, which are connected to a guard ring or a dummy line 110surrounding the active area, are provided at an area A of the substrate10, i.e., at the area between the pads either 101 or 201 and the activearea.

[0070] In a meanwhile, the shorting bars 102 and 202 may be locatedinside a cutting line 11 of the substrate, differently as illustrated inFIG. 3.

[0071]FIG. 4 shows an enlarged view of the area A in FIG. 3. In FIG. 4,the cutting line 11, at which the substrate 10 is cut to remove theshorting bar 102, a boundary line 21 which corresponds to anothersubstrate 20 oppisite the substrate 10, and the active area line 41 areshown by dotted lines. The shorting bar 102 is located inside thecutting line 11, the pads 101 connected to the shorting bar 102 arelocated between the cutting line 11 and the boundary line 21, and wires100 extend from the pads 101 toward the active area. A seal area 90occupied by a sealant for combing two substrates is located between theboundary line 21 and the active area line 41. The guard ring or dummyline 110, made of metal, is placed between the seal area 90 and theactive area line 41, and electrostatic discharge protection diodecircuits 120, spark inducing circuits or electrostatic charging circuits140 and 150 are connected respective wires 100 and the dummy line 110.

[0072] Now, the electrostatic discharge protection diode circuits 120are described with reference to FIG. 5.

[0073] A gate electrode and a drain electrode of a TFT Q1 are connectedto the dummy line 110, and a source electrode is connected to the wire100. There is provided another TFT Q2 having a gate electrode and adrain electrode connected to the wire 100, and a source electrodeconnected to the dummy line 110. Since the gate and the drain electrodesof the TFTs Q1 and Q2 are connected to each other, the TFTs Q1 and Q2serves as diodes. As a result, the TFTs Q1 and Q2 are interconnected ina back-to-back mode between the dummy line 110 and the wire 100.

[0074] The TFTs Q1 and Q2 generally includes an amorphous silicon havinghigh resistance, while the wire 100 is made of a material having towresistance such as a metal. Therefore, the amount of electrostaticcharges which enter the dummy line 110 may be smaller than the amount ofelectrostatic charges which enter the wire 100. As a result, it isdifficult to completely protect the LCD substrate against electrostaticcharges having a large electric charge value using only the circuitshown in FIG. 5.

[0075] The spark inducing circuit and the electrostatic charging circuitmay help the electrostatic discharge protection.

[0076] As previously mentioned in FIG. 4, spark inducing circuits 130and first electrostatic charging circuits 140 are connected to theadjacent wires 100 at the positions between the seal area 90 and thepads 101, and second electrostatic charging circuits 150 are connectedto the wires 100 at the positions between the seal area 90 and theactive area 41. Therefore, the electrostatic charges are effectivelydischarged.

[0077] However, since the spark inducing circuits 130 and theelectrostatic charging circuits 140 and 150 are located outside the areaenclosed by the seal area 90, circuit defects such as erosion by air ordamage by external shocks may occur.

[0078]FIG. 6 is an enlarged view of the area A in FIG. 3 according to asecond preferred embodiment of the present invention. In the secondembodiment, electrostatic discharge protection circuits are locatedinside the area enclosed by the seal area 90.

[0079] As shown in FIG. 6, spark inducing circuits 130 are connected towires 100 at the position between the seal area 90 and the active arealine 41, and electrostatic discharge protection diode circuits 120 areconnected to the wires 100 as in the previous embodiment. First andsecond electrostatic charging circuits (not shown) may be providedinside the area enclosed by the seal area 90.

[0080] A various types of the spark inducing circuits 130 according tothe preferred embodiments are shown in FIGS. 7 to 11. First to fourthspark inducing circuits ST1, ST2, ST3 and ST4 will be described withreference to FIGS. 7 to 10, respectively, the first to fourth sparkinducing circuits ST1, ST2, ST3 and ST4 representing the different typesof spark inducing circuits.

[0081]FIG. 7 illustrates the first spark inducing circuit ST1. As shownin the drawing, the first spark inducing circuit ST1 includes a pair ofTFTs Q3 and Q4, which are connected between two adjacent wires 100 inseries, and two capacitors C1 and C2. That is, gate electrodes of theTFTs Q3 and Q4 are connected to each other, a source or a drainelectrode of one of the TFTs is connected to a source or a drainelectrode of the other TFT, and electrodes of the capacitors C1 and C2are respectively connected to one of the adjacent two wires 10 and tothe gate electrodes of the TFTs Q3 and Q4. A plurality of the firstspark inducing circuit ST1 are connected to the adjacent two wires 100in parallel.

[0082] The operation of the first spark inducing circuit ST1 will bedescribed hereinafter. If electrostatic charges generated from the pads101 enter into the first spark inducing circuit ST1, sparks occur in theTFTs of the first spark inducing circuit ST1 to extinguish theelectrostatic charges. As a result, the TFTs in the active area areprotected from the electrostatic charges. In the case that electrostaticcharges are generated in the wires 100, since they are charged in thecapacitors C1 and C2 to turn on the TFTs, the electrostatic charges aredispersed through the wires 100.

[0083] In the first spark inducing circuit ST1, if more than two TFTsare connected between the wires 100 in series, the increase of thecurrent between the wires 100 can be effectively reduced.

[0084]FIG. 8 shows the second spark inducing circuit ST2. As shown inthe drawing, the second spark inducing circuit ST2 includes a TFT Q5 anda capacitor C3. A gate electrode and a drain electrode of the TFT Q5 areelectrically connected to each other and a source electrode of the TFTQ5 is connected to the wire 100. The capacitor C3 is connected betweenthe gate electrode and a common voltage. Vcom which is also connected toa common electrode (not shown). A plurality of the second spark inducingcircuits ST1 may be connected to each of the wires 100.

[0085] In this embodiment, the common electrode is used as a storageelectrode, but an additional electrode may be used as the storageelectrode.

[0086]FIG. 9 shows the third spark inducing circuit ST3. As shown in thedrawing, the structure of the third spark inducing circuit ST3 issubstantially the same as the second spark inducing circuit ST2.However, the third spark inducing circuits ST3 has a plurality of TFTsQ6 and Q7 and only one capacitor C4. The gate electrodes and the drainelectrodes of the TFTs Q6 and Q7 are connected to each other and to thecapacitor C4, and the source electrodes of the TFTs Q6 and Q7 areconnected to the wire 100. The operation of the third spark inducingcircuit ST3 is almost the same as that of the second spark inducingcircuit ST2.

[0087] As the same as in the second spark inducing circuit the commonelectrode is used as a storage electrode, but an additional electrodemay be used as the storage electrode.

[0088] The first to the third spark inducing circuits ST1, ST2 and ST3may be located inside the area enclosed by the seal area 90.

[0089]FIG. 10 shows the fourth spark inducing circuit ST4.

[0090] As shown in the drawing, a dummy wire or a guard ring including adummy gate line 111 and a dummy data line connected to the dummy gateline 111 is provided, and a TFT Q8 is formed on the dummy gate line 111.A gate, a source and a drain electrodes of the TFT Q8 are connected tothe dummy gate line 111, a data line 200, and an electrode of acapacitor C5 which has another electrode connected to the dummy gateline 111.

[0091] In the fourth spark inducing circuit ST4, if electrostaticcharges are transmitted to the dummy gate line 111, the capacitor C5 ischarged to turn on the TFT Q8, and the electrostatic charges generatedfrom the dummy gate line 111 and from the dummy data line 112, aredispersed to the data line 200 and the dummy wires. In the case that thecharge value of the electrostatic charges is large, the TFT Q8 is brokendown by sparks occurring in the same, thereby extinguishing theelectrostatic charges.

[0092] In the first to fourth spark inducing circuits ST1, ST2, ST3 andST4, the energy due to the electrostatic charges is changed to jouleenergy by burning the TFTs such that the electrostatic charges do notaffect the circuits in the active area.

[0093]FIG. 11 shows the first electrostatic charging circuit 140 of FIG.4. As shown in the drawing, the first electrostatic charging circuitincludes capacitors C6 and C7 which are connected to each other inseries between two adjacent wires. A plurality of the circuits areconnected to adjacent wires 100 in parallel. The first electrostaticcharging circuit may be located outside the area enclosed by the sealarea 90, and it stores electrostatic charges to reduce the level of thesame.

[0094]FIG. 12 shows the second electrostatic charging circuit 150 ofFIG. 4. Here, the second electrostatic charging circuit finally removesthe remaining electrostatic charges so that they do not enter the activearea. As shown in the drawing, capacitors a plurality of capacitors C8are connected between the respective wires 100 and a common electrodevoltage Vcom. The second electrostatic charging circuit 150 storeselectrostatic charges and reduces the level of the same.

[0095] The fourth spark inducing circuit ST4 of FIG. 10 will bedescribed in more detail hereinafter with reference to FIG. 13illustrating a layout view of the fourth spark inducing circuit ST4 ofFIG. 10, and FIG. 14 showing a cross sectional view taken along lineXIV-XIV′ of FIG. 13.

[0096] As shown in FIGS. 13 and 14, the fourth spark inducing circuitincludes a TFT pattern and a capacitor. The TFT includes a gateelectrode which is a portion of a dummy gate line 111, a gate insulatingfilm 3, a semiconductor pattern 700 formed on the gate insulating film 3opposite the gate electrode, a source electrode which is a branch of adata line 200 and a metal pattern 103 serving as a drain electrode. Thesource and drain electrodes overlap the either edges of thesemiconductor pattern 700. A transparent conductive layer 6 which isconnected to the metal pattern 103 and overlaps the dummy gate line 111to form a storage capacitor. A dummy data line 112 is formed in avertical direction at the position outer than the fourth spark inducingcircuits, and connected to all the dummy gate lines 111 throughconnecting patterns 5.

[0097] In detail, a plurality of dummy gate lines 111 are formed on asubstrate 10 in a horizontal direction, a gate insulating film 3 isformed thereon, and semiconductor patterns 700 are formed on the gateinsulating film 3 opposite the dummy gate line 111. A dummy data line112 and a plurality of data lines 200 are formed on the gate insulatingfilm 3 in a vertical direction and the data lines 200 overlap one edgesof the semiconductor patterns 700. A plurality of metal patterns 103,overlapping the opposite edges of the semiconductor patterns 700 areformed on the gate insulating film 3, and ohmic contact layers 710 forimproving electric contact characteristics are formed between thesemiconductor patterns 700 and the data lines 200 and the metal patterns103. An interlayer insulating film 4 covers the dummy data line 112, thedata lines 200 and the semiconductor patterns 700. Contact holes C1 andC3 are pierced in the interlayer insulating film 4, and contact holes C2in the gate insulating filme 3 and the interlayer insulating film 4expose the dummy gate line 111. Transparent conductive patterns 6 areformed on the interlayer insulating film 4 and connected to the metalpattern 103 through the contact hole C3, and transparent contactpatterns 5 on the interlayer insulating film 4 are connected to thedummy data line 112 and the respective dummy gate lines 111 through thecontact holes C1 and C2.

[0098] In this embodiment, it is desirable that the distance between thedummy gate lines 111 is smaller than the distance between the gate linesinside the active area to reduce the area occupied by the dummy wires.

[0099] In the above spark inducing circuit having the TFT and thecapacitor structures, when electrostatic charges enter the circuitthrough the data line 200 or the dummy data line 112, the electrostaticcharges charge between the capacitor transparent conductive pattern 700and the dummy gate line 111, and disappears. The electrostatic chargesgenerating from the dummy data line 200 may be changed into joule heatenergy by burning the TFT, and may disappear.

[0100]FIG. 15 is another layout view of the fourth spark inducingcircuit, and FIG. 16 is a cross sectional view taken along line XVI-XVI′of FIG. 15, in which an enlarged metal pattern 104 is substituted forthe transparent conductive pattern for the capacitor. In this structure,the metal pattern 104 is enlarged to overlap the dummy gate line 111such that a predetermined storage capacitance is formed between themetal pattern 104 and the dummy gate line 111. The extinguishing ofelectrostatic charges is performed identically as in the fourth sparkinducing circuit ST4 described with reference to FIGS. 13 and 14.

[0101] To prevent electrostatic charges from entering an active area, itis preferable to form dummy pixels having a structure similar with thepixels in the active area.

[0102]FIG. 17 shows a layout view of a dummy pixel for dischargingelectrostatic charges according to a preferred embodiment of the presentinvention, and FIG. 18 is a cross sectional view taken along the lineXVIII-XVIII′ of FIG. 17.

[0103] As shown in the drawings, a gate line or a dummy gate line 100 isformed on the first substrate 10 in a horizontal direction. The portionof the gate line or the dummy gate line 100 functions as a dummy gateelectrode. A gate insulating layer film 3 covers the dummy gate line100, and a dummy amorphous silicon layer 700 is formed on the gateinsulating film 3 over the dummy gate electrode. A dummy data line 110is formed on the gate insulating film 3 in a vertical direction. Thedummy gate line 100 and the dummy data line 110 cross each other anddefine a dummy pixel DP. The dummy pixel may be defined by the crossingof the gate line and the dummy gate line or of the dummy data line andthe dummy gate line.

[0104] A dummy source electrode 113, which branches from the dummy dataline 110, overlaps an edge of a doped amorphous silicon layer 710, and adummy drain electrode 114 overlaps another edge of the doped amorphoussilicon layer 710 at the opposite side of the dummy source electrode113. A highly doped amorphous silicon layer 710 is formed at the contactsurface of the dummy electrodes 113 and 114 and the dummy amorphoussilicon layer 710.

[0105] A width of the dummy source and drain electrodes 113 and 114 isequal to the width of the channel formed in the dummy amorphous silicon700, and a distance DL between the dummy source electrode 113 and thedummy drain electrode 114 is a channel length DL. Here, the width of thedummy source and drain electrodes 113 and 114 is different from thewidth of the source and the drain electrode formed in the pixel, and thelength between the dummy source electrode 113 and the dummy drainelectrode 114 is different from the length between the source and thedrain electrode formed in the pixel.

[0106] As described above, to induce electrostatic charges into thedummy pixel, it is preferable that the ratio of the channel width to thechannel length in the dummy pixel is more than twice that of the ratioof the channel width to the channel length formed in the active area.

[0107] A passivation film 4 is formed on the dummy data line 110 and thedummy amorphous silicon layer 700, and a contact hole C4 is formed inthe passivation film 4 to expose the dummy drain electrode 114. A pixelelectrode 300, which is connected to the dummy drain electrode 114through the contact hole C4, is made of indium-tin-oxide (ITO) on thepassivation film 4. The pixel electrode 300 partially overlaps theadjacent dummy gate line 100.

[0108] An alignment film 7 covering the passivation film 4 is formed onthe first substrate 10. A black matrix 400, having an opening area atthe region corresponding to the dummy pixel DP, is formed on the side ofthe second substrate 11 facing the first substrate 10. A color filter500, overlapping the edges of the black matrix 400, is formed in thepixel region DP. Further, a transparent conductive common electrode 600and an alignment film 8 are, in this order, formed over the color filter500 and the black matrix.

[0109] Although the black matrix 400 is formed in the second substrate11 in the LCD according to the present invention, it is possible to formthe same in the first substrate 10. In this embodiment, the dummy gateline 100 and the dummy data line 110 are formed outside the active areato prevent electrostatic charges from entering into the active area. Inaddition, a plurality of the dummy TFTs may be formed in the dummypixel.

[0110]FIG. 19 is a layout view of a dummy pixel for dischargingelectrostatic charges according to another preferred embodiment of thepresent invention. As shown in the drawing, the structure of thedischarging dummy pixel is substantially identical to the structure ofthe dummy pixel shown in FIG. 17, but the dummy gate electrode 101,which is connected to the dummy gate line 100, is extended into thedummy pixel region. Moreover, three (i.e., a plurality) of sourceelectrodes 115, 116 and 117 are connected to the dummy data line 110,and dummy drain electrodes 125, 126 and 127, which respectivelycorrespond to the dummy source electrodes 115, 116 and 117, areconnected to the dummy pixel electrode 301 through contact holes C5, C6and C7.

[0111] A width DW1 of the first dummy source and drain electrodes 115and 125 is narrower than a width DW2 of the second dummy source anddrain electrode 116 and 126, and the width DW2 of the second dummysource and drain electrodes 116 and 126 is narrower than a width DW3 ofthe third dummy source and drain electrodes 117 and 127. With thisstructure, all distances DL between the dummy source electrodes 115, 116and 117 and the dummy drain electrodes 125, 126 and 127 are the same.However, it is possible to form these distances differently.

[0112] Pixel defects in the active area can be prevented by changing thestructure of the dummy TFT as described above and by quickly inducingelectrostatic charges to the dummy TFT in the dummy pixel.

[0113] Another discharging pattern for preventing electrostatic chargesfrom entering the active area will be described hereinafter. FIG. 20shows a layout view of a electrostatic charge discharging patternaccording to a first preferred embodiment of the present invention, FIG.21 shows a cross sectional view taken along line XXI-XXI′ of FIG. 20,and FIG. 22 is a perspective view of a capacitor which is formed on anend of the electrostatic charge discharging pattern.

[0114] A data line or a dummy data line 110 is formed on a gateinsulating film 3 over a substrate 10, and an amorphous silicon pattern704 for discharging electrostatic charges is formed on the gateinsulating film 3. The first electrode pattern 118, which overlaps anedge of the amorphous silicon pattern 704, is extended from the dataline or the dummy data line 110, and the second electrode pattern 128overlaps another edge of the amorphous silicon pattern 704 at theopposite side of the first electrode pattern 118. The ends of the firstand the second electrode patterns 118 and 128 are tapered to a point anda doped amorphous silicon pattern 710, such as an Ohmic contact layer,is formed at the contact surface of the first and the second electrodepatterns 118 and 128 and the amorphous silicon pattern 704. Apassivation film 4 is formed over the dummy data line 110, and the firstand the second electrode patterns 118 and 128; and a contact hole C8 isformed in the passivation film 4 to expose the second electrode pattern128. An ITO pattern 302 for the capacitor is formed on the passivationfilm 4 and overlaps the second electrode pattern 128. The ITO pattern302 for the capacitor is connected to the second electrode pattern 128through the contact hole C8.

[0115] In other words, the discharging pattern includes the amorphoussilicon pattern 704, the ITO pattern 302 for the capacitor for storingelectrostatic charges, and the first and the second electrode patterns118 and 128 which interlink the ITO pattern 302 and the amorphoussilicon pattern 704 to the dummy data line 110. in the LCD having thisdischarging pattern, electrostatic charges generated in the dummy dataline 110 often passes into the ITO pattern 302 through the amorphoussilicon pattern 302 and the second electrode pattern 128, so that theamorphous silicon does not breakdown The reason that the tunnelingeffect is superior to the breakdown effect is that the first and thesecond electrode patterns 118 and 128 are pointedly formed so that theelectrostatic charges are moved to the ends of the electrode patterns118 and 128, rather than to other portions.

[0116] As shown in FIG. 22, the ITO pattern 302 of the dischargingpattern corresponds to a common electrode 600 of an upper color filtersubstrate, facing the common electrode. Liquid crystal material LC isinterposed between the ITO pattern 302 and the common electrode 600 sothat the a storage capacitor Cst is formed in the end portion of thedischarging pattern. Since the electrostatic charges moving to the ITOpattern 302 for the capacitor are stored in the storage capacitor, theTFT in the active area is not affected by the electrostatic charges.

[0117]FIG. 23 shows a layout view of a electrostatic charge dischargingpattern according to a second preferred embodiment of the presentinvention. The structure of the electrostatic charge discharging patternof the second embodiment is similar to the structure of theelectrostatic charge discharging pattern of the first embodiment, butmore than two discharging devices are connected to the ITO pattern 302and the dummy data line 10 in parallel.

[0118] As shown in FIGS. 21 to 23, the first discharging device, whichincludes the first amorphous silicon pattern 704 and the first and thesecond electrode patterns 118 and 128, and the second dischargingdevice, which includes the second amorphous silicon pattern 705 and thethird and the fourth electrode patterns 118 and 129, are formed on agate insulating film 3. The first and the second discharging devices areconnected to the dummy data line 110 in parallel. Contact holes C8 andC9 to expose the second and the fourth electrode pattern 128 and 129 aremade in the passivation film 4, and the second and the fourth electrodepatterns 128 and 129 are connected to the ITO pattern 302 for thecapacitor through the contact holes C8 and C9.

[0119] As described in the electrostatic charge discharging pattern ofthe first embodiment, the ends of the first to the fourth electrodepattern 118, 128, 119 and 129 are pointedly formed. The first and thethird electrode patterns 118 and 119 respectively face the second andthe fourth electrode patterns 128 and 129. The first and the secondpatterns 118 and 128 are formed on the first 5 amorphous silicon pattern704, and the third and fourth patterns 119 and 129 are formed on thesecond amorphous silicon pattern 705. Thus, the electrostatic chargesflowing through the dummy data line 110 are discharged to the ITOpattern 302 for the capacitor through the pointed portion and stored inthe capacitor. The number of the discharging devices D1 and D2 which areconnected to the dummy data line 110 may be increased as required.

[0120]FIG. 24 shows a layout view of a electrostatic charge dischargingpattern according to a third preferred embodiment of the preventinvention. As shown in FIG. 24. the second electrode pattern 128 of thefirst discharging devices D1 and the fourth electrode pattern 129 of thesecond discharging devices D2 are connected to be adjacent to other datalines 120. The number of the discharging devices may be increased asrequired.

[0121] The structures of the electrostatic charge discharging patternsof the first to third embodiments described above have advantages indischarging electrostatic charges generated in the assembly step, theliquid crystal injection step, or the visual test step, since thecapacitor is formed after the upper and the lower substrates for the LCDare assembled.

[0122] Referring now to FIG. 25, shown is a layout view of aelectrostatic charge discharging pattern according to a fourth preferredembodiment of the present invention. As shown in the drawing, thestructure of the electrostatic charge discharging pattern of the fourthembodiment is almost the same as that of the first electrostatic chargedischarging pattern of the first embodiment, but the dummy metal line130 is formed on the substrate 10 in a horizontal direction. The dummymetal line 130 is grounded and overlaps the ITO pattern 302 for thecapacitor through a gate insulating film and a passivation film.Therefore, a capacitor is formed between the ITO pattern 302 and thedummy metal line 130 for when electrostatic charges move from the firstelectrode pattern 118 to the second electrode pattern 128 and the ITOpattern 302 by a tunneling effect in the amorphous silicon pattern 704.

[0123] The electrostatic charge discharging pattern of the fourthembodiment can discharge electrostatic charges more effectively becauseone more capacitor is formed in the step of forming wires in thesubstrate.

[0124] Now, a manufacturing method of the electrostatic chargedischarging patterns will be described hereinafter with references toFIGS. 21 to 25, and FIGS. 26A to 26F.

[0125] As shown in FIG. 26A, a metal layer for gate wires is depositedon a substrate 10 and patterned to form a gate line and a dummy gateline 100 respectively inside and outside. In the case of theelectrostatic charge discharging pattern of the fourth preferredembodiment, a dummy metal line 130 is formed outside an active area inparallel with the gate and the dummy gate line 100 in this step.

[0126] As shown in FIG. 26B, a gate insulating film 3 is deposited withsilicon nitride or silicon oxide. Next, an amorphous silicon and a dopedamorphous silicon are deposited and then patterned to form an amorphoussilicon pattern 704 for discharging electrostatic charges and a dopedamorphous silicon layer 710 outside the active area.

[0127] Subsequently, as shown in FIG. 26C, a metal layer for data wiresis deposited and patterned to form a data line, a dummy data line 110,the first electrode pattern 118. and the second electrode pattern 128.Where two or more discharging devices are formed, a plurality of pairsof electrode patterns 118, 128, 119, 129 are formed in this step. Thedoped amorphous silicon material, which is externally exposed, is thenremoved.

[0128] As shown in FIGS. 26D and 26E, a passivation film 4 is depositedand then the gate insulating film 3 and the passivation film 4 arepatterned to form contact holes C8 and C9 to expose the second and thefourth electrode pattern 128 and 129. As shown in FIG. 27F, an ITO isdeposited and patterned to form an ITO pattern 302 for a capacitor.

[0129] Next, another circuit for preventing the damage of the substrateby an electrostatic discharge will be described with reference to FIG.27.

[0130]FIG. 27 is another equivalent circuit of a circuit for preventingelectrostatic charges, which is connected to a portion of A in FIG. 3,according to a third preferred embodiment of the present invention.

[0131] As shown in FIG. 27, a first resistor R1 and a capacitor areconnected to each other in series between a data line 200 and a dummygate line 111, and the capacitor and an adjacent data line 200 of thedata line 200 are connected in series by a second resistor R2. The dummygate line 111 is electrically connected to a dummy data line 112 formedoutside the data line 200.

[0132] The electrostatic charges generated along the data line 200passes through the resistors R1 and R2 to disperse in a moment. Theelectrostatic charges generated to the dummy data line 112 moves alongthe dummy gate line 111 and stores to the capacitor C1 formed by thedata line 200 and the dummy gate fine 111.

[0133] The disappearance of the electrostatic charges will be describedwith reference to FIGS. 28 and 29.

[0134]FIG. 28 is a layout view of the pattern of the circuit in FIG. 27,and FIG. 29 is a cross sectional view taken along line XXIX-XXIX′ ofFIG. 28.

[0135] In general, since the device for protecting a substrate fromelectrostatic charges should be formed in narrow area between an activearea and pads, there is a limitation in minimizing the electrostaticcharge capacitance by increasing the capacitance of the capacitor. Inthis embodiment, a semiconductor pattern as a resistance, which connectsa capacitor to two adjacent data lines at the same time, is used toincrease the ability of dispersing the static electrity.

[0136] As shown in FIGS. 28 and 29, a plurality of gate lines (notshown) are formed on a transparent insulating substrate 10 in ahorizontal direction, at least one dummy gate line 11 is formed outsidethe gate line in the horizontal direction, and a gate insulating film 3covers the gate lines and the dummy gate line 111.

[0137] On the gate insulating film 3, a plurality of semiconductorpattern 707 and 708 are formed near the dummy gate line 111 with anamorphous silicon material, and a plurality of data lines 200 areformed. Two or more semiconductor patterns 707 and 708 are locatedbetween the two adjacent data lines 200. If one of the patterns is nameda first semiconductor pattern 707, and the other of the patterns isnamed a second semiconductor pattern 708, a first electrode 12 connectedto the data line 200, and a second electrode 13 facing the firstelectrode 12 respectively overlap the both sides of the firstsemiconductor pattern 707. Moreover, a third electrode 15 connected tothe other adjacent data line 200, and a fourth electrode 14 facing thethird electrode 15 respectively overlap the both sides of the secondsemiconductor pattern 708. An Ohmic contact layer for improving thecontact characteristic intermediates on the surface where the first, thesecond, the third and the fourth electrodes 12, 13, 15 and 14 contactsthe first and the second semiconductors 707 and 708.

[0138] At least one dummy data line 112 is formed outside the data line200 in parallel with the data line 200.

[0139] A passivation film 4 covers the data lines 200 and the dummy datalines 112, and contact holes C1, C2, C3, and C4, through which the dummydata line 112, the end of the dummy gate line 111, the second and thefourth electrodes 13 and 14 are exposed, are made in the passivationfilm 4.

[0140] A connecting pattern 5, which overlap the dummy data line 112 andthe dummy gate line 111, is formed on the passivation film 4 to connectthe dummy data line 112 and the gate line 111. A pattern for a capacitor9, which overlaps the second and the fourth electrodes 13 and 14 and thedummy gate line 111, is formed to connect the second and the fourthelectrodes 13 and 14 though the contact holes C3 and C4. The connectingpattern 5 and the pattern for the capacitor 9 may be made of atransparent indium-tin-oxide (ITO).

[0141] As mentioned above, since the dummy gate line 111 is connected tothe dummy data line 112, the electrostatic charges generated along thedummy data line 112 is transmitted to the dummy gate line 111 and isstored between the pattern for the capacitor 9 and the dummy gate line111 The electrostatic charges generated along the data line 200 losesits energy by passing through the first and the second semiconductorpatterns 707 and 708 to be transmitted to the pattern for the capacitor9, or by demolishing the first and the second semiconductor patterns 707and 708.

[0142]FIG. 30 is a layout view of the pattern of the circuit forpreventing electrostatic charges which is connected to a portion of A inFIG. 3 according to a fourth embodiment of the present invention, andFIG. 31 is a cross sectional view taken along line XXXI-XXXI′ FIG. 30.

[0143] As shown in FIGS. 30 and 31, fifth electrodes 109 arerespectively formed under the first and the semiconductor patterns 707and 708, so another capacitance is formed between the fifth electrodes109 and the first and the second semiconductor patterns 707 and 708.

[0144] The rest structures of the circuit are the same as in the thirdembodiment.

[0145]FIG. 32 is a layout view of the circuit for preventing anelectrostatic discharge which is connected to A portion in FIG. 3according to a fifth preferred embodiment of the present invention, inwhich dummy gate lines do not cross data lines and comprise a pluralityof patterns divided with respect to the data lines

[0146] As shown in FIG. 32, each of the patterns of the dummy gate lines111 is formed along the data line 200 between two the adjacent datalines 200, and overlaps several capacitor patterns 9 at a time, sosufficient capacitance can be obtained.

[0147] In this embodiment, the dummy gate line 111 is electricallyfloated.

[0148] Now, a manufacturing method of the LCD, in which damage by anelectrostatic discharge can be minimized, will be described hereinafterwith reference to FIGS. 33 and 34.

[0149]FIG. 33 shows a perspective view of an LCD showing a state inwhich a thin film transistor substrate and a color filter substrate areassembled to each other, and FIG. 34 shows a flow chart showing amanufacturing method of an LCD according to a present invention.

[0150] As shown in FIGS. 33 and 34, in STEP 1, a plurality of wires 100are formed on a transparent insulating substrate 10, and a shorting bar102, which links all the wires 100 and the pads 101 for contacting withexternal driving circuits, is formed outside the wires 100. In thisstep, electrostatic charge dispersing circuits, such as the diodes, thespark inducing circuits, the electrostatic charging circuits and thedischarging patterns. are formed to complete the TFT substrate 10 and acolor filter substrate, having a color filter and a common electrode,are formed.

[0151] Next, in STEP 2, the TFT substrate 10 and the color filtersubstrate 11 are cut to form each substrate, the substrates 10 and 11are disposed opposing one another, then liquid crystal material isinjected between the substrates 10 and 11. Electrostatic charges,generating in the step of cutting the substrates 10 and 11 and in thestep of injecting the liquid crystal material, are dispersed by theshorting bar 102.

[0152] In STEP 3, a hole used to inject the liquid crystal material issealed and then the shorting bar 102 is removed by a grinding process.In STEP 4, test signals are applied to each wire 105 to detect defectsin the LCD substrate. In this test, it is possible to perform a varietyof tests by applying different test signals to each of the wires 100 byusing probes which contact to each of the pads 101. Electrostaticcharges generated in this step extinguished in the spark inducingcircuits, electrostatic charging circuit, and discharging patterns.

[0153] After the test, STEP 5 is performed. In STEP 5, polarizers 1 and2 are attached on outer surfaces of the LCD substrates where there areno defects. In STEP 6, driving circuits are connected to the pads of theLCD. Generally, electrostatic charges easily generate in the step ofattaching the polarizers 1 and 2. In this method, the electrostaticcharges are effectively dispersed by the spark inducing circuit and theelectrostatic charging circuit, so that the electrostatic charges can beprevented from entering into the active area.

[0154] Unlike the conventional method, in this manufacturing method ofthe LCD, since the steps of cutting the substrate, injecting the liquidcrystal, and sealing the injection hole are performed with the shortingbar 102 present. the LCD substrate is protected from electrostaticcharges generated in the process. In addition, since the polarizers 1and 2 are attached on substrates which pass the visual test,manufacturing costs are reduced.

[0155] As described above, in the LCD according to the presentinvention, a dummy line is added outside the active area, a plurality ofelectrostatic charge dispersing circuits are connected to the dummyline, and the electrostatic charge dispersing circuit is made having asuitable structure to effectively discharge electrostatic charges. Thus,electrostatic charges can be prevented from entering into the activearea.

[0156] In addition, since the electrostatic charge dispersing circuitsare left remaining after the shorting bar is removed and the expensivepolarizers are attached after the visual test, damage to the LCD by anelectrostatic discharge is minimized and manufacturing costs aredecreased.

[0157] In the drawings and specification, there have been disclosedtypical preferred embodiments of the invention and, although specificterms are employed, they are used in a generic and descriptive senseonly and not for purpose of limitation, the scope of the invention beingset forth in the following claims.

What is claimed is:
 1. A liquid crystal display substrate comprising: afirst insulating substrate; a plurality of pixel electrodes fordisplaying images provided on the first substrate; a plurality ofswitching elements connected to the pixel electrodes; a plurality ofwires farmed on the first substrate and connected to the switchingelements; and a plurality of spark inducing circuits which are connectedbetween the wires adjacent to each other and extinguish electrostaticcharges generated on the first substrate by generating sparks responsiveto the generated electrostatic charges.
 2. A liquid crystal displaysubstrate according to claim 1 further comprising a sealant which isformed on the first substrate and seals the first substrate and a secondsubstrate opposing the first substrate, and wherein the spark inducingcircuit is located outside an area enclosed by the sealant.
 3. A liquidcrystal display substrate according to claim 1 wherein the sparkinducing circuit comprises: a plurality of thin film transistorsconnected between the adjacent wires in series, and having gateelectrodes which are interconnected, and two capacitors, each having afirst electrode connected to the gate electrode, and a second electrodeconnected to one of the respective wires.
 4. A liquid crystal displaysubstrate according to claim 1 wherein the spark inducing circuitcomprises: a thin film transistor having a drain electrode connected toone of the wires, and a gate and a source electrodes connected to eachother; and a capacitors which is connected between the gate electrode ofthe thin film transistor and a first voltage.
 5. A liquid crystaldisplay substrate according to claim 1 wherein the spark inducingcircuit comprises: a plurality of thin film transistors having drainelectrodes connected to one of the wires and gate electrodes and sourceelectrodes which are interconnected; and a capacitor which is connectedbetween the gate electrode and a first voltage.
 6. A liquid crystaldisplay substrate according to claim 1, further comprising a firstelectrostatic charging circuit which is connected between the adjacenttwo wires and stores and extinguishes electrostatic charges generated inthe wires.
 7. A liquid crystal display substrate according to claim 6wherein the first electrostatic charging circuit comprises twocapacitors connected to each other in series.
 8. A liquid crystaldisplay substrate according to claim 7 further comprising a secondelectrostatic charging circuit which is connected between the adjacenttwo wires and in parallel to the first electrostatic charging circuit.9. A liquid crystal display substrate according to claim 7, furthercomprising a sealant which is formed on the first substrate and sealsthe first substrate and a second substrate opposing the first substrate,and wherein the first electrostatic charging circuit is located outsidean area enclosed by the sealant.
 10. A liquid crystal display substrateaccording to claim 1 further comprising a sealant which is formed on thefirst substrate and seals the first substrate and a second substrateopposing the first substrate, and wherein the spark inducing circuit islocated inside an area enclosed by the sealant.
 11. A liquid crystaldisplay substrate according to claim 10 further comprising a dummy wireformed inside the area enclosed by the sealant, and wherein the sparkinducing circuit comprises: a thin film transistor having a gateelectrode connected to the dummy wire and a source electrode connectedto the wire. and a drain electrode; and a capacitor connected betweenthe dummy wire and the drain electrode
 12. A liquid crystal displaysubstrate comprising: a first insulating substrate; a plurality of pixelelectrodes for displaying images provided on the first substrate; aplurality of switching elements connected to the pixel electrodes; aplurality of wires which are formed on the first substrate and connectedto the switching elements; and an electrostatic charging circuitconnected between the wires adjacent to each other and storing andextinguishing electrostatic charges generated in the wires.
 13. A liquidcrystal display substrate according to claim 12 wherein theelectrostatic charging circuit comprises a capacitor including a firstelectrode which is a portion of one of the wires and a second electrode.14. A liquid crystal display substrate according to claim 12 furthercomprising a sealant which is formed on the first substrate and sealsthe first substrate and a second substrate opposing the first substrate,and wherein the electrostatic charging circuit is formed located insidean area enclosed by the sealant.
 15. A liquid crystal display substrateaccording to claim 1 further comprising a shorting bar which connects toall the wires and which is formed inside a cutting line of thesubstrate.
 16. A liquid crystal display substrate comprising: aplurality of gate lines which are formed on a substrate; a gateinsulating film covering the gate lines; a plurality of data lines whichare formed on the gate insulating film and vertically intersect the gatelines; at least a dummy gate line and a data dummy line whichrespectively link all the gate lines and all the data lines, the dummygate line covered with the gate insulating film: a thin film transistorhaving a gate electrode which is connected to the dummy gate line, asource electrode which is connected to either the data line or the dummydata line, and a drain electrode: and a capacitor electrode which isconnected to the drain electrode and overlaps the dummy gate line.
 17. Aliquid crystal display substrate according to claim 16, wherein thecapacitor electrode comprises a transparent conductive film connected tothe drain electrode through a contact hole in the gate insulating filmover the drain electrode.
 18. A manufacturing method of a liquid crystaldisplay substrate comprising the steps of: forming a plurality of liquidcrystal display panel regions having thin film transistors, pixelelectrodes, wires and electrostatic charge dispersing circuits on afirst insulating substrate; forming shorting bars which link the wiresin each of the panel regions; forming a cutting line for dividing theliquid crystal display panel regions on the first substrate such thatthe shorting bar is located inside the cutting line; aligning a secondsubstrate with the first substrate; sealing the first and the secondsubstrates; cutting the first substrate along the cutting line to divideinto a plurality of liquid crystal display panels; injecting a liquidcrystal material into the liquid crystal display panel through aninjection hole, sealing the injection hole; removing the shorting bars;detecting defects in the liquid crystal display panel; and attachingpolarizers on the liquid crystal display panel.
 19. A liquid crystaldisplay comprising: a first insulating substrate; a plurality of gatelines which are formed on the first substrate; a plurality of data lineswhich intersect the gate lines to define a plurality of pixel regions; aplurality of pixel electrodes which are formed in the pixel regions; aplurality of first thin film transistors formed in the pixel regions,each thin film transistor includes a gate, a source and a drainelectrodes respectively connected to one of the gate lines, one of thedata lines and one of the pixel electrodes; a plurality of dummy datalines which are formed outside an active area including the pixelregions, and intersect the gate lines to define a plurality of firstdummy pixel regions; a plurality of dummy gate lines which are formedoutside the active area and intersect the data lines or the dummy datalines to define a plurality of second dummy pixel regions; a dummy pixelelectrode which is formed in the first or the second dummy pixel region;a dummy thin film transistor which is connected to the gate line, thedata line, the dummy gate line and either the dummy data line in thedummy pixel region, and has a ratio of a channel width to a channellength is larger than the first thin film transistors; and a secondsubstrate which opposes the first substrate.
 20. A liquid crystaldisplay according to claim 19, further comprising a black matrix formedon either the first or the second substrate.
 21. A liquid crystaldisplay according to claim 20 wherein the dummy pixel electrode iscovered with the black matrix.
 22. A liquid crystal display according toclaim 19 wherein the ratio of the channel width to the channel length ofthe dummy thin film transistor is more than twice the first thin filmtransistors.
 23. A liquid crystal display comprising: a first insulatingsubstrate; a plurality of gate lines which are formed on the firstsubstrate; a plurality of data lines which intersect the gate lines todefine a plurality of pixel regions; a plurality of pixel electrodeswhich are formed in the pixel regions; a plurality of first thin filmtransistors formed in the pixel regions, each thin film transistorincludes a gate, a source and a drain electrodes respectively connectedto one of the gate lines, one of the data lines and one of the pixelelectrodes; a plurality of dummy data lines which are formed outside anactive area including the pixel regions, and intersect the gate lines todefine a plurality of first dummy pixel regions; a plurality of dummygate lines which are formed outside the active area and intersect thedata lines or the dummy data lines to define a plurality of second dummypixel regions; a dummy pixel electrode which is formed in the first orthe second dummy pixel region; and a plurality of dummy thin filmtransistors which are formed in one of the first or the second dummypixel regions and are connected to the gate line, the data line, andeither the dummy gate line or the dummy data line.
 24. A liquid crystaldisplay according to claim 23 wherein the dummy thin film transistorshave different values of the ratio of the channel width to the channellength.
 25. A liquid crystal display according to claim 23 wherein thedummy thin film transistors are connected to the dummy pixel electrode.26. A liquid crystal display comprising: a insulating substrate; aplurality of wires which are formed on the substrate; and a firstdischarging pattern which is connected to one of the wires and has asemiconductor pattern, wherein electrostatic charges are dischargedthrough the channel generated in the semiconductor pattern by tunnelingeffect.
 27. A liquid crystal display according to claim 26 furthercomprising a storage capacitor formed between the semiconductor patternand a first voltage.
 28. A liquid crystal display according to claim 27further comprising a plurality of second discharging patterns areconnected to the wire in parallel to the first discharging pattern. 29.A liquid crystal display according to claim 28 wherein the first and thesecond discharging patterns are connected between the adjacent two wiresin parallel.
 30. A liquid crystal display comprising: an insulatingsubstrate; an insulating film which is formed on the substrate; a wirewhich is formed on the substrate in a first direction; an amorphoussilicon pattern for discharging electrostatic charges which is formednear the wire; a first electrode which extends from the wire andcontacts an edge of the amorphous silicon pattern; and a secondelectrode which contacts another edge of the amorphous silicon pattern,wherein electrostatic charges are discharged from the first electrode tothe second electrode through the amorphous silicon pattern by tunnelingeffect.
 31. A liquid crystal display according to claim 30 wherein theends of the first and the second electrodes are tapered to a point. 32.A liquid crystal display according to claim 31 further comprising: apassivation film which covers the first and the second electrodes andhave a contact hole exposing the second electrode; and a conductivepattern for a capacitor which is formed on the passivation film andconnected to the second electrode through the contact hole, whereinelectrostatic charges are stored in a storage capacitor including theconductive pattern and a common electrode formed on a correspondingsubstrate facing the substrate.
 33. A liquid crystal display accordingto claim 32 further comprising a metal line which is formed on thesubstrate in a second direction, and overlaps the conductive pattern.34. A manufacturing method of a liquid crystal display comprising of thesteps: depositing a first metal layer on an insulating substrate;patterning the first metal layer to form gate wires; forming a gateinsulating film, an amorphous silicon layer, a doped amorphous siliconlayer and a amorphous silicon pattern for discharging electrostaticcharges; depositing a second metal layer, and patterning the secondmetal layer to form data wires, and first and second electrodes fordischarging electrostatic charges connected to the amorphous siliconpattern.
 35. A manufacturing method of a liquid crystal displayaccording to claim 34 wherein the first electrode extends from the datawire, the end of the first electrode is pointedly formed, and thepointed end overlaps the edge of the amorphous silicon pattern for thedischarge of electrostatic charges.
 36. A manufacturing method of aliquid crystal display according to claim 35 wherein the end of thesecond electrode is pointedly formed and the second electrode overlapsan edge of the amorphous silicon pattern at an opposite side of thefirst electrode.
 37. A manufacturing method of a liquid crystal displayaccording to claim 36, further comprising the steps of: depositing apassivation film on the data wire and the first and the secondelectrodes; and patterning the gate insulating film and the passivationfilm to form a contact hole exposing the second electrode.
 38. Amanufacturing method of a liquid crystal display according to claim 37,further comprising the steps of: depositing a conductive layer; andpatterning the conductive layer to form a pixel electrode and aconductive pattern for a capacitor which is connected to the secondelectrode through the contact hole.
 39. A manufacturing method of aliquid crystal display according to claim 38, further comprising thestep of patterning the first metal layer to form a dummy metal line fordischarging electrostatic charges.
 40. A liquid crystal display having aplurality of pixels comprising: a plurality of gate lines and aplurality of data lines which intersect each other to define the pixels;at least one dummy gate line which are formed in parallel with the gateline and located outside an active area which includes the pixels; afirst resistor and a capacitor which are connected in series between afirst data line of the data lines and the dummy gate line; and a secondresistor which is connected to the capacitor and to a data line adjacentto the first data line.
 41. A liquid crystal display according to claim40, further comprising at least one dummy data fine which is formedoutside the active area in parallel with the data lines, andelectrically connected to the dummy gate line.
 42. A liquid crystaldisplay comprising: a plurality of gate lines formed on a substrate; atleast one dummy gate line formed on the substrate outer of the gatelines; a gate insulating film covering the gate lines and the dummy gateline; a plurality of data lines which are formed on the gate insulatingfilm and intersect the gate lines and the dummy gate lines; a pluralityof first semiconductor patterns which are formed on the gate insulatingfilm and respectively connected to a first data line of the data lines;a plurality of second semiconductor patterns which are formed on thegate insulating film and respectively connected to a second data line ofthe data lines adjacent to the first data line; a passivation filmcovering the data lines and the first and the second semiconductorpatterns; and at least one capacitor patterns which are formed on thepassivation film, overlap the dummy gate lines and, and are electricallyconnected to the first and the second semiconductor patterns.
 43. Aliquid crystal display according to claim 42, further comprising atleast one dummy data line which is formed on the substrate in parallelwith the data lines and electrically connected to the dummy gate line.44. A liquid crystal display according to claim 43, further comprising aconnecting pattern which is formed on the passivation film, overlaps theend of the dummy gate line and the dummy data line, and is connected tothe dummy gate line and the dummy data line through contact holes in thepassivation film.
 45. A liquid crystal display according to claim 42,wherein the capacitor patterns are located in plural between adjacenttwo data lines, the dummy gate line comprises a plurality of dummypatterns separated from each other with respect to the data lines, andeach of the dummy patterns overlaps the capacitor patterns at a timebetween adjacent two data lines.
 46. A liquid crystal display accordingto claim 45, wherein the dummy pattern is floated.
 47. A liquid crystaldisplay according to claim 42, further comprising a first and a secondconnecting patterns which are formed on the gate insulating film andrespectively connect the first semiconductor pattern to the capacitorpattern and the second semiconductor pattern to the capacitor pattern.48. A liquid crystal display according to claim 47, wherein thecapacitor pattern is made of an indium-tin-oxide.
 49. A liquid crystaldisplay according to claim 42, wherein the first and the secondsemiconductor patterns are made of an amorphous silicon.
 50. A liquidcrystal display according to claim 42, further comprising electrodepatterns which are formed between the substrate and the gate insulatingfilm and located under the first and the second semiconductor patterns.